| Home |
| Step | Action | Comment | Reference |
|---|---|---|---|
| 0 | DISABLE MASKABLE INTERRUPTS | Within the CPU | Page 5-116 (line 311) |
| 1 | 8088 CPU TEST | If the test fails, halt the CPU. | Page 5-116 |
| 2 | DISABLE NON-MASKABLE INTERRUPTS | Disable non-maskable interrupts (NMIs) from reaching the CPU. A diagram is here. | Page 5-116 (line 371) |
| 3 | DMA CHAN 0/1 PAGE REGISTER | Zero the page register used by DMA channels 0 and 1. See note 16. | Page 5-116 (line 372) |
| 4 | DISABLE MDA/CGA VIDEO | See note 18. | Page 5-116 (lines 373-377) |
| 5 | 8255 OPERATION - PART 1 OF 2 | 8255 PPI chip. Set the operation of ports A and B to output mode. See note 11. (Later, in step 20, port A will be switched back to input mode - see note 15.) |
Page 5-116 (lines 378-379) |
| 6 | 8255 OUTPUTS | 8255 PPI chip. Now that port B is in output mode, set the port B lines to various states, specifically, set to A5 hex. One of those port B lines, PB7, is set high to so as to disable the keyboard shift register chip. That enables port A to be used by the POST for checkpoints. See note 15. |
Page 5-116 (lines 380-382) |
| 7 | CHECKPOINT 1 | Generate checkpoint 1. Click here for information about checkpoints. | Page 5-116 (lines 385-386) |
| 8 | ROM CHECKSUM TEST I | Verify that the 8-bit checksum of the fourth and final 8 KB block in U18 (i.e. the 8 KB block at FE000) is 00. If verification fails, halt the CPU. |
Page 5-116 (lines 387-396) |
| 9 | CHECKPOINT 2 | Generate checkpoint 2. Click here for information about checkpoints. | Page 5-116 (lines 409-410) |
| DISABLE DMA CONTROLLER | Disable the 8237 DMA controller chip. | Page 5-116 (lines 411-412) | |
| 10 | TEST TIMER 1 | Channel #1 on 8253 timer chip. Channel #1 is used in RAM refresh process. If the test fails, halt the CPU. | Page 5-116 (lines 413-442) |
| 11 | CHECKPOINT 3 | Generate checkpoint 3. Click here for information about checkpoints. | Page 5-116 (lines 446-447) |
| 12 | TEST DMA CONTROLLER | Test the 8237 DMA controller chip. If the test fails, halt the CPU. | Page 5-117 (lines 451-472) |
| 13 | START RAM REFRESH | RAM refresh is done via dummy DMA transfers. Step 13.1: Initialise channel #1 on 8253 timer, setting a divisor of 18. That results in one output pulse per approx. 15 µs. See here and here. Step 13.2: Initialise and start channel #0 on DMA controller. |
Page 5-117 (lines 474-491) |
| 13a | DMA CONTROLLER | Set the mode on channel 1 of the DMA controller. | Page 5-117 (lines 492-493) |
| 13b | HOT TIMER 1 | Verify that no output from channel #1 on 8253 timer has appeared at DMA channel #0 request (DREQ0) yet. If it has, halt the CPU. | Page 5-117 (lines 495-498) |
| 13c | DMA CONTROLLER | Set the mode on channels 2 and 3 of the DMA controller. | Page 5-117 (lines 499-502) |
| 14 | EXPANSION I/O BOX - ENABLE | Write 1 to port 213h. If an extender card for the IBM 5161 Expansion Unit is present in the 5160, that action enables the extender card to
communicate with the 5161. Presumably, this enabling is done now so that any RAM in the 5161 is zeroed in step 17. See note 7 for more information. |
Page 5-117 (lines 513-515) |
| 15 | BASE 16 KB RAM - TEST | If a cold boot, test first 16 KB of RAM. If the test fails, loop forever, generating checkpoint 4 within that loop. |
Page 5-117 |
| 16 | BASE 16 KB RAM - ZERO | Zero the contents of the first 16 KB of RAM. | Page 5-118 (lines 531-533) |
| 17 | DETERMINE TOTAL RAM FITTED / ZERO RAM |
Conventional memory only. Size determined by a write/read to the first two addresses of each successive 16KB block. That is flawed design. See note 9. After each block is 'discovered', the RAM in that block is zeroed. Only goes as high as A0000 (640 KB). Done on both cold and warm boots. For cold boots, the act of writing to each RAM address will appropriately set/reset the parity bit of each address. See note 6. |
Page 5-118 (lines 534-555) |
| 18 | SET UP STACK SEG AND SP | Set up the stack segment (SS) and stack pointer (SP). SS set to 0030, SP set to 0100, i.e. motherboard address 00400. | Page 5-118 (lines 557-561) |
| 19 | 8259 INITIALISATION | Initialise the 8259 interrupt controller chip. | Page 5-118 |
| 20 | 8255 OPERATION - PART 2 of 2 | Step 20.1: Change port A operation of the 8255 PPI chip from output mode to input mode. Step 20.2: Via the the 8255 PPI chip, enable the keyboard shift register chip. (Done by the KBD_RESET subroutine on line 619.) See note 15 for more information. |
Page 5-118 (lines 617-619) |
| IF REQUESTED, LOAD DIAG. CODE | Take the clock pin in the motherboard's keyboard DIN connector LOW for 20 ms. (Done by the KBD_RESET subroutine.) If the attached device responds with the byte of AAh, the attached device is a keyboard. If the attached device responds with the byte of 65h, the attached device is a special IBM device that supplies diagnostic code to the 5160 via the keyboard port. If the latter, jump to the routine ('MFG_BOOT') that loads the diagnostic code via the keyboard port, then executes the code. |
Page 5-118 (lines 619-624) | |
| DETECT MT MODE | If the previous step did not detect a keyboard, then see if the data pin in the motherboard's keyboard DIN connector has been intentionally grounded. If grounded, that is IBM using some sort of test kit to signal that the POST is to go into 'Manufacturing Test' mode, in which case, set the 'Manufacturing Test' mode flag. NOTE: The 'Manufacturing Test' mode flag is inspected in some following tests. NOTE: Blinking of the LED on IBM's test kit is not initiated until later in the 5160's POST - see 'BLINK LED' below. |
Page 5-118 (lines 625-632) | |
| 21 | INIT/START VIDEO CARD | STEP 1 OF 3: (lines 645-656) (a) Reset any MDA card (card may not be present) by sending 1 to control port on MDA, i.e. I/O port 3B8h. (b) Reset any CGA card (card may not be present) by sending 0 to control port on CGA, i.e. I/O port 3D8h. STEP 2 OF 3: (lines 658-763) Examine video switches on motherboard (SW1:5 and SW1:6) to see which type of video card is selected. If MDA selected: - (a) Set the MDA card for 80x25 mode. (Send MDA-unique bytes to the MDA card's CRT controller chip. [I/O ports 3Bx]) - (b) If warm boot, go to (d). - (c) It is a cold boot. Test the MDA card's video RAM. If that fails, beep 1 long then 2 short, then go to (e). - (d) Do a 'video line test'. If that fails, beep 1 long then 2 short. - (e) "Set mode and display cursor" - (f) Go on to do step 3. If CGA selected: - (a) As applicable, set the CGA card to 40x25 or 80x25 mode. (Send CGA-unique bytes to the CGA card's CRT controller chip. [I/O ports 3Dx]) - (b) If warm boot, go to (d). - (c) It is a cold boot. Test the CGA card's video RAM. If that fails, beep 1 long then 2 short, then go to (e). - (d) Do a 'video line test'. If that fails, beep 1 long then 2 short. - (e) "Set mode and display cursor" - (f) Go on to do step 3. STEP 3 OF 3: (lines 765-780) Irrespective of the type of video card selected, look for BIOS expansion ROM's in address block C0000 - C7FFF. Those will be video ROM's in EGA/VGA cards. If one found (first 2 bytes are 55/AA), verify that its 8-bit checksum is 00, and if that verification passes, call the initialisation code in the ROM. If the verification fails, then display the address of faulty ROM followed by "ROM" (e.g. "C0000 ROM"). See note 5 for more information. |
Page 5-119 |
| 22 | 8259 TEST | 8259 interrupt controller chip. Step 22.1: Test the IMR register. Step 22.2: Look for hot interrupts. If the test fails, display a "101" error then halt the CPU. NOTE: This is a very limited test of the 8259. NOTE: The 101 error can also be generated by two other tests - See test 'TEST/SET TIMER 0' and test 'DMA TC0'. |
Page 5-120 |
| 23 | TEST/SET TIMER 0 | Channel #0 on 8253 timer chip. This is what generates IRQ 0 (system timer). If the test fails, display a "101" error then halt the CPU. If the test passes, set channel #0 output to a square wave of approx. 18.2 Hz. See here and here. NOTE: The test relies on the ability of the 8259 to process IRQ 0 and the ability of the 8088 to process interrupts from the 8259. See here. NOTE: The 101 error can also be generated by two other tests - See test '8259 TEST' and test 'DMA TC0'. |
Page 5-120 |
| 24 | KEYBOARD TEST | Diagram here. If there is a problem, display a "301" error. See note 13 for possible 301 causes. NOTE: This test is skipped if the POST is in 'Test Chamber' mode or 'Manufacturing Test' mode. |
Page 5-121 |
| 25 | INTERRUPT VECTORS | Set up interrupt vector table. | Page 5-121 (lines 911-931) |
| BLINK LED | If the POST is in 'Manufacturing Test' mode, then "BLINK LED" on IBM's test kit. See here. | Page 5-121 (lines 935-939) | |
| 26 | EXPANSION I/O BOX - TEST | If an extender card for the IBM 5161 Expansion Unit is fitted in the 5160, then test communications with the 5161. If the test fails, display an "1801" error. See here for information about how the POST determines that an extender card is present. See the 1801 section of here for possible 1801 causes. |
Page 5-122 |
| 27 | ADDITIONAL RAM TEST | Conventional memory only. Test RAM past 16 KB. The upper limit was determined earlier in step 17. Only do this test on cold boot. If the test of RAM fails, display failing address followed by bit error pattern, followed by " 201". Example: "30000 80 201". |
Page 5-123 |
| DMA TC0 | Verify that the TC0 status bit in the 8237 DMA controller chip is on. This test is only done on a cold boot. If the test fails, display a "101" error then halt the CPU. NOTE: Two earlier tests can also generate a 101 error, however this 101 appears AFTER the on-screen check of RAM is done. NOTE: If desired, this particular 101 error can be triggered by grounding pin 13 of the 8253 timer chip - see here. |
Page 5-123 (lines 1072-1079) | |
| 28 | EXPANSION ROM SEARCH | Look for BIOS expansion ROM's in address range C8000 to F5FFF (see note 2). For each one found (first 2 bytes are 55/AA), verify that the 8-bit checksum of the ROM (size is in third byte) is 00. More info here. If verification passes, call the initialisation code in the ROM. If verification fails, then display address of faulty ROM followed by " ROM" (e.g. "C8000 ROM"). |
Page 5-124 See note 1 for more info. |
| 29 | ROM CHECKSUM TEST II | Step 29.1: Verify that the 8-bit checksum of U19 (i.e. 8 KB at F6000) is 00. If not 00, display "F6000 ROM". Step 29.2: Verify that the 8-bit checksum of the first 8 KB block in U18 (i.e. 8 KB at F8000) is 00. If not 00, display "F8000 ROM". Step 29.3: Verify that the 8-bit checksum of the second 8 KB block in U18 (i.e. 8 KB at FA000) is 00. If not 00, display "FA000 ROM". Step 29.4: Verify that the 8-bit checksum of the third 8 KB block in U18 (i.e. 8 KB at FC000) is 00. If not 00, display "FC000 ROM". See note 4 for more information. |
Page 5-124 |
| 30 | FLOPPY (DISKETTE) DRIVE ATTACHMENT TEST |
Step 30.1: Test communication with floppy controller card. On failure, display a "601" error. Step 30.2: Via controller, turn on spindle motor of floppy drive 0. Step 30.3: Via controller, with 'RECAL REQUIRED' set, move heads of floppy drive 0 to track 1. On failure, display a "601" error. Step 30.4: Via controller, with 'RECAL REQUIRED' set, move heads of floppy drive 0 to track 34. On failure, display a "601" error. Step 30.5: Via controller, turn off spindle motor of floppy drive 0. This test can pass if head stepping is not happening properly - see note 14. NOTE: 'RECAL REQUIRED' tells the controller that before it moves the heads to the target track, it is to first move the heads back to track 0. NOTE: After successful execution, the heads are left at track 34. At POST end, the heads will go back to track 0 as part of a boot attempt. NOTE: When DOS later loads (step 40), DOS will assign drive letter A (a logical drive) to floppy drive 0 (a physical drive). NOTE: This test is skipped if the POST is in 'Test Chamber' mode. |
Page 5-124 |
| 31 | SET UP KEYBOARD BUFFER | Page 5-124 | |
| 32 | 8259 - ENABLE TIMER/KYB INT | 8259 interrupt controller. Enable interrupts IRQ 0 (system timer) and IRQ 1 (keyboard). | Page 5-124 (lines 1214-1216) |
| 33 | PASS/FAIL INDICATION | Examine BP to see whether or not an error occured earlier. If no error then beep 1 short, otherwise beep 2 short then display "ERROR. (RESUME = F1 KEY)" then wait for the F1 key to be pressed. NOTE: The 1 short beep is not done if the POST is in 'Manufacturing Test' mode. |
Page 5-125 (lines 1217-1238) |
| 34 | LOOP POST | If the POST is in 'Test Chamber' mode (i.e. if switch 1 on switch block SW1 is in the ON position), restart the computer. | Page 5-93 (lines 1235-1238) |
| 35 | CLEAR SCREEN | Page 5-125 (lines 1239-1241) | |
| 36 | DETERMINE LPT (PARALLEL) PORTS | Check for parallel ports at the following I/O addresses, in that order: 3BC, 378, 278 When a port is found, put the base address of the port into the BIOS Data Area (see here). |
Page 5-125 (lines 1245-1261) |
| 37 | DETERMINE COM (SERIAL) PORTS | Check for serial ports at the following I/O addresses, in that order: 3F8, 2F8 When a port is found, put the base address of the port into the BIOS Data Area (see here). |
Page 5-125 (lines 1262-1286) |
| 38 | JOYSTICKS | Are two joysticks present? See here | Page 5-125 (lines 1287-1294) |
| 39 | ENABLE NON-MASKABLE INTERRUPTS | A diagram is here. | Page 5-125 (line 1304-1305) |
| 40 | DO BOOTSTRAP | Essentially, the boot order is: 1. floppy drive 0 2. hard drive 0 (if XT-class hard disk controller present) 3. cassette BASIC |
Page 5-125 (line 1307) |
| Step | Action | Comment | Reference |
|---|---|---|---|
| 0 | DISABLE MASKABLE INTERRUPTS | Within the CPU | Page 5-85 (line 143) |
| 1 | 8088 CPU TEST | If the test fails, halt the CPU. | Page 5-85 |
| 2 | DISABLE NON-MASKABLE INTERRUPTS | Disable non-maskable interrupts (NMIs) from reaching the CPU. A diagram is here. | Page 5-85 (line 202) |
| 3 | DMA CHAN 0/1 PAGE REGISTER | Zero the page register used by DMA channels 0 and 1. See note 16. | Page 5-85 (line 203) |
| 4 | DISABLE MDA/CGA VIDEO | See note 18. | Page 5-85 (lines 204-208) |
| 5 | 8255 OPERATION - PART 1 OF 2 | 8255 PPI chip. Set the operation of ports A and B to output mode. See note 11. (Later, in step 20, port A will be switched back to input mode - see note 15.) |
Page 5-85 (lines 209-210) |
| 6 | 8255 OUTPUTS | 8255 PPI chip. Now that port B is in output mode, set the port B lines to various states, specifically, set to A5 hex. One of those port B lines, PB7, is set high to so as to disable the keyboard shift register chip. That enables port A to be used by the POST for checkpoints. See note 15. |
Page 5-85 (lines 211-215) |
| 7 | CHECKPOINT 1 | Generate checkpoint 1. Click here for information about checkpoints. | Page 5-85 (lines 216-217) |
| 8 | ROM CHECKSUM | Verify that the combined 8-bit checksum of U18 and U19 (i.e. 64KB block at F0000) is 00. If verification fails, halt the CPU. |
Page 5-85 |
| 9 | CHECKPOINT 2 | Generate checkpoint 2. Click here for information about checkpoints. | Page 5-86 (lines 241-242) |
| DISABLE DMA CONTROLLER | Disable the 8237 DMA controller chip. | Page 5-86 (lines 243-244) | |
| 10 | TEST TIMER 1 | Channel #1 on 8253 timer chip. Channel #1 is used in RAM refresh process. If the test fails, halt the CPU. | Page 5-86 (lines 246-274) |
| 11 | CHECKPOINT 3 | Generate checkpoint 3. Click here for information about checkpoints. | Page 5-86 (lines 278-279) |
| 12 | TEST DMA CONTROLLER | Test the 8237 DMA controller chip. If the test fails, halt the CPU. | Page 5-86 (lines 280-307) |
| 13 | START RAM REFRESH | RAM refresh is done via dummy DMA transfers. Step 13.1: Initialise channel #1 on 8253 timer, setting a divisor of 18. That results in one output pulse per approx. 15 µs. See here and here. Step 13.2: Initialise and start DMA controller. |
Page 5-86 (lines 309-326) |
| 13a | DMA CONTROLLER | Set the mode on channel 1 of the DMA controller. | Page 5-86 (lines 327-328) |
| 13b | HOT TIMER 1 | Verify that no output from channel #1 on 8253 timer has appeared at DMA channel #0 request (DREQ0) yet. If it has, halt the CPU. | Page 5-86 (lines 330-333) |
| 13c | DMA CONTROLLER | Set the mode on channels 2 and 3 of the DMA controller. | Page 5-86 (lines 334-337) |
| 14 | DELAY | A delay to better cater for dynamic RAM chips. See note 12. | Page 5-87 (lines 347-350) |
| 15 | BASE 64 KB RAM - TEST | If a cold boot, test first 64 KB of RAM. If the test fails, loop forever, generating checkpoint 4 within that loop. |
Page 5-87 (lines 356-368) |
| 16 | BASE 64 KB RAM - ZERO | Zero the contents of the first 64 KB of RAM. | Page 5-87 (lines 369-371) |
| 17 | DETERMINE TOTAL RAM FITTED / ZERO RAM |
Size determined by a write/read to the first two addresses of each successive 16 KB block. That is flawed design. See note 9. After each block is 'discovered', the RAM in that block is zeroed. Only goes as high as A0000 (640KB). Done on both cold and warm boots. For cold boots, the act of writing to each RAM address will appropriately set/reset the parity bit of each address. See note 6. |
Page 5-87 (lines 372-399) |
| 18 | SET UP STACK SEG AND SP | Set up the stack segment (SS) and stack pointer (SP). SS set to 0030, SP set to 0100, i.e. motherboard address 00400. | Page 5-87 (lines 401-405) |
| 19 | 8259 INITIALISATION | Initialise the 8259 interrupt controller chip. | Page 5-87 |
| 20 | 8255 OPERATION - PART 2 of 2 | Step 20.1: Change port A operation of the 8255 PPI chip from output mode to input mode. Step 20.2: Via the the 8255 PPI chip, enable the keyboard shift register chip. (Done by the KBD_RESET subroutine on line 462.) See note 15 for more information. |
Page 5-88 (lines 460-462) |
| IF REQUESTED, LOAD DIAG. CODE | Take the clock pin in the motherboard's keyboard DIN connector LOW for 20 ms. (Done by the KBD_RESET subroutine.) If the attached device responds with the byte of EAh, the attached device is an enhanced keyboard. If the attached device responds with the byte of AAh, the attached device is a 'normal' keyboard. If the attached device responds with the byte of 65h, the attached device is a special IBM device that supplies diagnostic code to the 5160 via the keyboard port. If the latter, jump to the routine ('MFG_BOOT') that loads the diagnostic code via the keyboard port, then executes the code. |
Page 5-88 (lines 462-472) | |
| DETECT MT MODE | If the data pin in the motherboard's keyboard DIN connector is grounded, then set the 'Manufacturing Test' mode flag. | Page 5-88 (lines 474-483) | |
| 21 | INIT/START VIDEO CARD | STEP 1 OF 3: (lines 496-507) (a) Reset any MDA card (card may not be present) by sending 1 to control port on MDA, i.e. I/O port 3B8h. (b) Reset any CGA card (card may not be present) by sending 0 to control port on CGA, i.e. I/O port 3D8h. STEP 2 OF 3: (lines 509-617) Examine video switches on motherboard (SW1:5 and SW1:6) to see which type of video card is selected. If MDA selected: - (a) Set the MDA card for 80x25 mode. (Send MDA-unique bytes to the MDA card's CRT controller chip. [I/O ports 3Bx]) - (b) If warm boot, go to (d). - (c) It is a cold boot. Test the MDA card's video RAM. If that fails, beep 1 long then 2 short, then go to (e). - (d) Do a 'video line test'. If that fails, beep 1 long then 2 short. - (e) "Set mode and display cursor" - (f) Go on to do step 3. If CGA selected: - (a) As applicable, set the CGA card to 40x25 or 80x25 mode. (Send CGA-unique bytes to the CGA card's CRT controller chip. [I/O ports 3Dx]) - (b) If warm boot, go to (d). - (c) It is a cold boot. Test the CGA card's video RAM. If that fails, beep 1 long then 2 short, then go to (e). - (d) Do a 'video line test'. If that fails, beep 1 long then 2 short. - (e) "Set mode and display cursor" - (f) Go on to do step 3. STEP 3 OF 3: (lines 619-634) Irrespective of the type of video card selected, look for BIOS expansion ROM's in address block C0000 - C7FFF. Those will be video ROM's in EGA/VGA cards. If one found (first 2 bytes are 55/AA), verify that its 8-bit checksum is 00, and if that verification passes, call the initialisation code in the ROM. If the verification fails, then display the address of faulty ROM followed by "ROM" (e.g. "C0000 ROM"). See note 5 for more information. |
Page 5-88 |
| 22 | 8259 TEST | 8259 interrupt controller chip. Step 22.1: Test the IMR register. Step 22.2: Look for hot interrupts. If the test fails, display a "101" error then halt the CPU. NOTE: This is a very limited test of the 8259. NOTE: The 101 error can also be generated by two other tests - See test '8259 TEST' and test 'DMA TC0'. |
Page 5-89 |
| 23 | TEST/SET TIMER 0 | Channel #0 on 8253 timer chip. This is what generates IRQ 0 (system timer). If the test fails, display a "101" error then halt the CPU. If the test passes, set channel #0 output to a square wave of approx. 18.2 Hz. See here and here. NOTE: The test relies on the ability of the 8259 to process IRQ 0 and the ability of the 8088 to process interrupts from the 8259. See here. NOTE: The 101 error can also be generated by two other tests - See test 'TEST/SET TIMER 0' and test 'DMA TC0'. |
Page 5-90 |
| 24 | KEYBOARD TEST | Diagram here. If there is a problem, display a "301" error. See note 13 for possible 301 causes. NOTE: This test is skipped if the POST is in 'Test Chamber' mode or 'Manufacturing Test' mode. |
Page 5-90 |
| 25 | INTERRUPT VECTORS | Set up interrupt vector table. | Page 5-90 (lines 766-787) |
| BLINK LED | If the POST is in 'Manufacturing Test' mode, then "BLINK LED" on IBM's test kit. See here. | Page 5-90 (lines 791-795) | |
| 26 | EXPANSION I/O BOX - TEST | If an extender card for the IBM 5161 Expansion Unit is fitted in the 5160, then test communications with the 5161. If the test fails, display an "1801" error. See the 1801 section of here. |
Page 5-91 |
| 27 | ADDITIONAL RAM TEST | Test RAM past 64 KB. Only do on cold boot. If the test fails, display failing address followed by bit error pattern, followed by " 201". Example: "30000 80 201". See note 10 for more info. |
Page 5-91 |
| DMA TC0 | Verify that the TC0 status bit in the 8237 DMA controller chip is on. This test is only done on a cold boot. If the test fails, display a "101" error then halt the CPU. NOTE: Two earlier tests can also generate a 101 error, however this 101 appears AFTER the on-screen check of RAM is done. NOTE: If desired, this particular 101 error can be triggered by grounding pin 13 of the 8253 timer chip - see here. |
Page 5-92 (lines 928-935) | |
| 28 | EXPANSION ROM SEARCH | Look for BIOS expansion ROM's in address block C8000 to EFFFF (see note 3). For each one found (first 2 bytes are 55/AA), verify that the 8-bit checksum of the ROM (size is in third byte) is 00. More info here. If verification passes, call the initialisation code in the ROM. If verification fails, then display address of faulty ROM followed by " ROM" (e.g. "C8000 ROM"). |
Page 5-92 See note 8 for more info. |
| 29 | FLOPPY (DISKETTE) DRIVE ATTACHMENT TEST |
Step 29.1: Test communication with floppy controller card. On failure, display a "601" error. Step 29.2: Via controller, turn on spindle motor of floppy drive 0. Step 29.3: Via controller, with 'RECAL REQUIRED' set, move heads of floppy drive 0 to track 34. On failure, display a "601" error. Step 29.4: Via controller, turn off spindle motor of floppy drive 0. Step 29.5: Setup diskette states for all floppy drives. On failure, display a "601" error. See note 17. This test can pass if head stepping is not happening properly - see note 14. NOTE: 'RECAL REQUIRED' tells the controller that before it moves the heads to the target track, it is to first move the heads back to track 0. NOTE: When DOS later loads (step 39), DOS will assign drive letter A (a logical drive) to floppy drive 0 (a physical drive). NOTE: This test is skipped if the POST is in 'Test Chamber' mode. |
Page 5-92 |
| 30 | SET UP KEYBOARD BUFFER | Page 5-93 | |
| 31 | 8259 - ENABLE TIMER/KYB INT | 8259 interrupt controller. Enable interrupts IRQ 0 (system timer) and IRQ 1 (keyboard). | Page 5-93 |
| 32 | PASS/FAIL INDICATION | Examine BP to see whether or not an error occured earlier. If no error then beep 1 short, otherwise beep 2 short then display "ERROR. (RESUME = F1 KEY)" then wait for the F1 key to be pressed. NOTE: The 1 short beep is not done if the POST is in 'Manufacturing Test' mode. |
Page 5-93 |
| 33 | LOOP POST | If the POST is in 'Test Chamber' mode (i.e. if switch 1 on switch block SW1 is in the ON position), restart the computer. | Page 5-93 (lines 1094-1097) |
| 34 | CLEAR SCREEN | Page 5-93 (lines 1098-1100) | |
| 35 | DETERMINE LPT (PARALLEL) PORTS | Check for parallel ports at the following I/O addresses, in that order: 3BC, 378, 278 When a port is found, put the base address of the port into the BIOS Data Area (see here). |
Page 5-93 (lines 1104-1120) |
| 36 | DETERMINE COM (SERIAL) PORTS | Check for serial ports at the following I/O addresses, in that order: 3F8, 2F8 When a port is found, put the base address of the port into the BIOS Data Area (see here). |
Page 5-93 (lines 1121-1136) |
| 37 | JOYSTICKS | Are two joysticks present? See here | Page 5-94 (lines 1146-1153) |
| 38 | ENABLE NON-MASKABLE INTERRUPTS | A diagram is here. | Page 5-94 (lines 1163-1164) |
| 39 | DO BOOTSTRAP | Essentially, the boot order is: 1. floppy drive 0 2. hard drive 0 (if XT-class hard disk controller present) 3. cassette BASIC |
Page 5-94 (line 1166) |
| Note 1 | Page 5-124: ROM_SCAN - The code that does the search. Page 5-169: ROM_CHECK - The code called to see if a particular ROM has an expected 8-bit checksum of 00. Page 5-126: ROM_ERR - The code called if a ROM's 8-bit checksum is bad (not 00). |
| Note 2 | Start signature of ROM checked for in 2K increments: C8000, C8800, C9000, --> F5800 Block end address incorrectly commented as "F4000" in source code. It should be "F6000". The last address checked is F5800. Based on the diagram here, it should have been EF800 (as per later BIOS revisions). Perhaps IBM was anticipating people replacing the 2764 with a 27256 that has custom ROM BIOS expansion code put into the first three quarters. |
| Note 3 | Start signature of ROM checked for in 2 KB increments: C8000, C8800, C9000, --> EF800 The last address checked is EF800, which makes sense because the 01/10/86 BIOS starts at F0000. Diagram here. |
| Note 4 | * In the reference, this is the routine labelled BASE_ROM_CHK (page 5-124). * On this motherboard (64/256), U18 is 32 KB sized and U19 is 8 KB sized. * No need to check fourth 8 KB block in U18 - was already done by step 8. |
| Note 5 | * The search for EGA/VGA video ROM's always happens, even if the motherboard's video switches are set for MDA or CGA. * EGA/VGA cards initialise themselves, via initialisation code in their ROM. * The initialisation code in some video ROM's produce their own error beeps. Example: IBM EGA cards can produce 1 long beep followed by 3 short beeps. |
| Note 6 | On power on of the computer, the contents of motherboard RAM will be somewhat random. That means that for a certain portion of addresses, the content of the parity bit will not reflect the parity of the combined data bits. After POST completion (non-maskable interrupts enabled), attempts to read from such addresses would result in a parity error. By writing (anything) to the addresses now, the parity bit at the address is appropriately set/reset. |
| Note 7 | Research revealed that this step is not required. And it is observed that this step disappears when the 01/10/86 revision of the IBM 5160 BIOS is introduced. For more information, see the 'Research' section at here. |
| Note 8 | Page 5-92: ROM_SCAN - The code that does the search. Page 5-101: ROM_CHECK - The code called to see if a particular ROM has an expected 8-bit checksum of 00. Page 5-95: ROM_ERR - The code called if a ROM's 8-bit checksum is bad (not 00). |
| Note 9 | The size determination process is flawed in design. Why? Because if the process encounters faulty RAM, the process incorrectly assumes that it has reached the end of RAM. |
| Note 10 | People have observed that this BIOS tests RAM faster than the earlier BIOS. The technical reason for the faster testing is that the earlier BIOS (11/08/82) writes/reads a byte at a time, whereas this BIOS (01/10/86) writes/reads a word at a time. 11/08/82: Use of STOSB and LODSB in STGTST_CNT routine (page 5-126 of reference) 01/10/86: Use of STOSW and LODSW in STGTST_CNT routine (page 5-97 of reference) |
| Note 11 | At power on (and after RESET released), the 8255 defaults to mode 0 operation for both groups, with all 3 ports (A, B and C) being inputs. So, even though the command sent to the 8255 is [Group_A_mode=0, Group_B_mode=0, Port_A=outputs, Port_B=outputs, Port_C_upper=inputs, Port_C_lower=inputs], the only result is that the port A and B lines change from inputs to outputs. |
| Note 12 | The following text from the Panasonic MN4164 datasheet is typical of dynamic RAM: Several cycles are required after power up or prolonged periods of RAS inactivity before proper device operation is acheived. Any 8 cycles which perform refresh are adequate for this purpose. |
| Note 13 | If the "301" is preceeded by a byte, e.g. "23 301", then the keyboard's self test is indicating to the POST that a key is 'stuck' down. The byte indicates which key (see here). If the "301" is not preceeded by a byte, then it's a general keyboard error. Possible causes: 1. AT class keyboard attached. That will not work. A PC/XT class keyboard is required. 2. No keyboard attached. 3. Faulty keyboard - broken wire in cable. 4. Faulty keyboard - wire loose in connector. 5. Faulty keyboard - chip failure. 6. Faulty motherboard - bad solder joint on DIN connector for keyboard. 7. Faulty motherboard - some cases of faulty keyboard circuitry. |
| Note 14 | The only form of head position feedback that the floppy drive electronics has, is a switch that detects whether or not the heads are at the first track, track 0. And so the drive really doesn't know if the heads got as far as track 34. For example, deteriorated lubrication on the drive's rails (resulting in improper head stepping) may mean that the heads only got as far as say, track 22. In that example, the drive is faulty (improper head stepping), but the 601 test is passing because the drive is unable to detect exact head position (except for the heads being on track 0). |
| Note 15 | The POST outputs checkpoint codes to I/O port 60h (0x60). That corresponds to port A on the 8255 PPI chip. During that period, 8255 port A is configured by the POST for output mode. Also during that period, presumably to avoid the possibility of chip damage, the POST disables the keyboard shift register chip (U27). See diagram here. After the POST has output the final checkpoint code, the POST switches 8255 port A back to input mode, and enables the keyboard shift register chip. Port A is then used to read keyboard data 'assembled' in the keyboard shift register. Click here for information about checkpoints. |
| Note 16 | Looking at the circuit diagram of the IBM 5160 motherboard: • Chip U10, a 74LS670, contains four page registers. • Page register 0 (mapped to port 80h) is unused (RB and RA cannot be 0 at the same time, because /DACK2 and /DACK3 cannot be 0 at the same time) • Page register 1 (mapped to port 81h) is used by DMA channel 2 (RB=0 and RA=1, because /DACK2=0 and /DACK3=1) • Page register 2 (mapped to port 82h) is used by DMA channel 3 (RB=1 and RA=0, because /DACK2=1 and /DACK3=0) • Page register 3 (mapped to port 83h) is used by DMA channels 0 and 1 (in both cases, RB=1 and RA=1, because /DACK2=1 and /DACK3=1) |
| Note 17 | Only in the 1986 dated motherboard BIOS'. Calls a subroutine named DSKETTE_SETUP. That subroutine is commented as, "This routine does a preliminary check to see what type of diskette drives are attached to the system." For each drive (drive count indicated by motherboard switches 7 and 8), one of the things done by the subroutine is see whether a drive is 40-track or 80-track. |
| Note 18 | Something else done is to set the high-resolution bit on the MDA. This is critical for IBM's MDA card - refer to IBM's technical document for the IBM MDA. |
